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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16505-2E
Proprietary 32-bit Microcontroller
CMOS
FR60 MB91310 Series
MB91F312A/FV310A
s DESCRIPTION
The FR families are lines of single-chip microcontrollers based on a 32-bit high-performance RISC CPU, incorporating a variety of I/O resources for embedded control applications which require high CPU performance for high-speed processing. The FR families are best suited for embedded applications which require high-performance CPU power for processing, such as TV and POP control. Based on the FR30/FR40 family CPU, this FR60 family is enhanced in bus access for use in faster applications.
s FEATURE
* FR CPU * 32-bit RISC, load/store architecture with a five-stage pipeline * Operating frequency: 40 MHz (using PLL at an oscillation frequency of 10 MHz) * 16 - bit fixed length instructions (basic instructions), 1 instruction per cycle * Instruction set optimized for embedded applications: Memory-to-memory transfer, bit manipulation, barrel shift etc. (Continued)
s PACKAGE
144-pin plastic LQFP
(FTP-144P-M08)
MB91310 Series
* Instructions adapted for high-level languages: Function entry/exit instructions, multiple-register load/store instructions * Register interlock functions: Facilitating coding in assemblers * On-chip multiplier supported at the instruction level. Signed 32-bit multiplication: 5 cycles. Signed 16-bit multiplication: 3 cycles * Interrupt (PC, PS save): 6 cycles, 16 priority levels * Harvard architecture allowing program access and data access to be executed simultaneously * Instruction prefetch function implemented by a four-word queue in the CPU * Instruction compatible with FR family * Bus interface This bus interface is used for macro connection. (USB, MS-IF, OSDC) * Operating frequency Max 20 MHz * 16-bit data input/output (Interface to the USB, MS-IF, and OSDC) * Chip-select signals can be output for completely independent eight areas allocatable in a minimum of 64 KB. The CS1, CS2, and CS3 areas are reserved as follows. CS0, CS4, to CS3 are Mnusable. CS1 area : USB host CS2 area : USB function CS3 area : MS-IF, OSDC * Basic bus cycle : 2 cycles * Programmable automatic wait cycle generator capable of inserting wait cycles for each area CS1, CS2 and CS3 are reserved; their settings are fixed. * Built-in RAM * 16 KB built RAM capacity * This RAM can be used as instruction RAM by writing instruction code as well as data. * DMAC (DMA Controller) * Connected to five channels (ch0, ch1 USB function; ch2 MS-IF). * 3 forwarding factors (internal peripheral/software) * Addressing using 32 - bit full addressing mode (increment, decrement, fixed) * Demand transfer, burst transfer, step transfer, or block transfer * Selectable transfer data size: 8-bit, 16-bit, or 32-bit * Bit search module (for REALOS) * Search for the position of the bit 1/0-changed first in one word from the MSB * Reload timer (including 1 channel for REALOS) * 16-bit PPG timer ch3 * The internal clock is optional from 2/8/32 en surroundings.
(Continued)
2
MB91310 Series
* UART * Full duplex double buffer * UART : 5 channels * With parity / no parity selection * Asynchronous (start - stop synchronized) or CLK - synchronous communications selectable * Internal timer for dedicated baud rate * External clock can be used as transfer clock * Assorted error detection functions (for parity, frame, and overrun errors) * I2C Interface * Four channels are incorporated. (ch3 can be used as two ports.) * Master/slave sending and receiving * Clock synchronization function * Detecting transmitting direction function * Bus error detection function * Arbitration function * Slave address and general call address detection function * Start condition repeat generation and detection function * 10 bit/7 bit slave address
* Standard mode (Max 100 Kbps)/High speed mode (Max 400 Kbps) supported * Interrupt controller * A total of five external interrupt lines are provided (1 nonmaskable interrupt pin (NMI) and 4 normal interrupt pins (INT3 to INT0). * Interrupt from internal peripheral devices. * Programmable priorities (16 levels) for all interrupts except the non - maskable interrupt * Available for wakeup from STOP mode * A/D converter * 10-bit resolution. 10 channels * Successive comparator type, conversion time : approx. 10 s * Conversion modes (Single conversion mode, Scan conversion mode) * Startup sources (software and external triggers) * PPG * 4 channels * Six-bit down-counter, 16-bit data register with cycle setting buffer * The internal clock is optional from 1/4/16/64 en surroundings. * PWC * One channel (input) incorporated * 16 bits up counter * Simple LFP digital filter incorporated * Timer * Lowpass filter eliminating noise below the clock setting * Capable of pulse width measurement according to fine settings using seven types of clock signals * Event count function based on pin input * Interval timer function using seven different clocks and one external input clock (Continued) 3
MB91310 Series
(Continued) * USB host function * U.S.B 1.0 Specification * 8 KB of internal RAM for parameters
* USB function * USB 1.1 compliant full-speed double buffering * CONTROL IN/OUT, BULK IN/OUT, INTERRUPT IN * OSDC function * High-quality OSDC integrated * Analog RGB interface (with internal DAC) * Digital RGB I/F * Internal dot clock generator PLL * Other internal times * 16-bit PPG timer ch3(u-timer) * Watch dog timer * I/O port * Max 72 ports * Other features * Internal oscillator circuit as clock source * INIT is prepared as a reset terminal. * Watchdog timer reset. Software reset. * Low power consumption modes supported: Stop mode and Sleep mode * Gear function * Built-in time base timer * Package : LQFP-144, 0.5 mm pitch, 20 mm x 20 mm * CMOS technology (0.25 m) * Supply voltage: Dual power supplies at 3.3 V 0.3 V, 2.5 V 0.2 V
THE I2C LICENSE : "Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips."
4
MB91310 Series
s PIN ASSIGNMENT
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109
DCKO VOB1 VOB2 VDDE VDDI VSS R2 R1 R0 G2 G1 G0 B2 B1 B0 UHP UHM UDP UDM VDDE VDDI X1B VSS X0B P74 P73 P72 P71 P70 ICD3 ICD2 ICD1 ICD0 ICS2 ICS1 ICS0
P01/SDA0 P02/SCL1 P03/SDA1 VDDE VDDI(PLL) X0 VSS X1 INIT P04/SCL2 P05/SDA2 P06/SCL3 P07/SCL4 P10/SDA3 P11/SDA4 P12/SI0 P13/SO0 P14/SCK0 P15/SI1 P16/SO1 P17/SCK1 P20/SI2 P21/SO2 P22/SCK2 P23/SI3 P24/SO3 P25/SCK3 P30/SI4/TIN0 P31/SO4/TIN1 P32/SCK4/TIN2 P33/TO0 P34/TO1 P35/TO2 P36/RIN P40/TMO0 P41/TMO1
37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72
DOCKI FH VSYNC HSYNC VGS CPO VSS VDDI (PLL) VDDR (2.5 V) VREF (1.1 V) VRO (2.7 k) RCOMP (0.1 F) ROUT VSSR VDDG (2.5 V) GCOMP (0.1 F) GOUT VSSG VDDB (2.5 V) BCOMP (0.1 F) BOUT VSSB AVCC AVRH AVSS/AVRL AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 P00/SCL0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
(TOP VIEW)
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
IBREAK ICLK TRST VSS VDDI VDDE NMI P65/INT3 P64/INT2 P63/INT1 P62/INT0 P61 P60/ATRG P57/TRG3 P56/TRG2 P55/TRG1 P54/TRG0 P53/TMI3 P52/TMI2 P51/TMI1 P50/TMI0 MD3 MD2 MD1 MD0 P47/PPG3 P46/PPG2 P45/PPG1 P44/PPG0 X1A VSS X0A VDDI VDDE P43/TMO3 P42/TMO2
5
MB91310 Series
s PIN DESCRIPTION
Pin no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Pin name DOCKI FH VSYNC HSYNC VGS CPO VSS VDDI (PLL) VDDR (2.5 V) VREF (1.1 V) VRO (2.7 k) RCOMP (0.1 F) ROUT VSSR VDDG (2.5 V) GCOMP (0.1 F) GOUT VSSG VDDB (2.5 V) BCOMP (0.1 F) BOUT VSSB AVCC AVRH AVSS/AVRL AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 Circuit type D D D D K K K K K K K K K E E E E E E E E E E Dot clock input Vertical synchronous output Horizontal synchronous input Vertical synchronous input Device Ground Charge pump output Dot clock PLL ground Dot clock PLL power supply D/A power supply for R Voltage reference input Resistor connection pin Capacitor connection pin R output (Analog) D/A Ground for R D/A power supply for G Capacitor connection pin G output (Analog) Device Ground for G D/A power supply for B Capacitor connection pin B output (Analog) D/A Ground for B A/D Power Supply A/D referense power supply A/D Ground Analog input Analog input Analog input Analog input Analog input Analog input Analog input Analog input Analog input Analog input Description
(Continued)
6
MB91310 Series
Pin no. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
Pin name P00 SCL0 P01 SDA0 P02 SCL1 P03 SDA1 VDDE VDDI (PLL) X0 VSS X1 INIT P04 SCL2 P05 SDA2 P06 SCL3 P07 SCL4 P10 SDA3 P11 SDA4 P12 SI0 P13 SO0 P14 SCK0 P15 SI1 P16 SO1
Circuit type C C C C A A B C C General-purpose port I2C clock pin General-purpose port I2C Data pin General-purpose port I2C Clock General-purpose port I2C Data pin 3.3 V Power Supply 2.5 V Power Supply 10-MHz oscillation pin Ground 10-MHz oscillation pin Initial (reset) pin General-purpose port I2C clock General-purpose port I2C Data pin General-purpose port N I2C clock General-purpose pors I2C clock General-purpose port N I2C data pin General-purpose port I2C data pin C C C C C General-purpose port UART0 serial input General-purpose port UART0 serial output General-purpose port UART0 clock input/output General-purpose port UART1 serial input General-purpose port UART1 serial output
Description
(Continued)
7
MB91310 Series
Pin no. 57 58 59 60 61 62 63
Pin name P17 SCK1 P20 SI2 P21 SO2 P22 SCK2 P23 SI3 P24 SO3 P25 SCK3 P30 SI4 TIN0 P31
Circuit type C C C C C C C General-purpose port UART1 clock input/output General-purpose port UART2 serial input General-purpose port UART2 serial output General-purpose port UART2 clock input/output General-purpose port UART3 serial input General-purpose port UART3 serial output General-purpose port UART3 clock input/output General-purpose port C UART4 serial input
Description
64
Reload timer 0 trigger input General-purpose port C UART4 serial output Reload timer 1 trigger input General-purpose port C UART4 clock input/output Reload timer 2 trigger input C C C C C C General-purpose port Reload timer 0 output General-purpose port Reload timer 1 output General-purpose port Reload timer 2 output General-purpose port PWC input General-purpose port Multi-function timer 0 output General-purpose port Multi-function timer 1 output
65
SO4 TIN1 P32
66
SCK4 TIN2 P33 TO0 P34 TO1 P35 TO2 P36 RIN P40 TMO0 P41 TMO1
67 68 69 70 71 72
(Continued)
8
MB91310 Series
Pin no. 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94
Pin name P42 TMO2 P43 TMO3 VDDE VDDI X0A VSS X1A P44 PPG0 P45 PPG1 P46 PPG2 P47 PPG3 MD0 MD1 MD2 MD3 P50 TMI0 P51 TMI1 P52 TMI2 P53 TMI3 P54 TRG0 P55 TRG1 P56 TRG2
Circuit type C C A A C C C C F F F F C C C C General-purpose port
Description Multi-function timer 2 output General-purpose port Multi-function timer 3 output 3.3 V power supply 2.5 V power supply 32 kHz oscillation pin Ground 32 kHz oscillation pin General-purpose port PPG0 output General-purpose port PPG1 output General-purpose port PPG2 output General-purpose port PPG3 output Mode Pins Mode Pins Mode Pins Mode Pins (ground) General-purpose port Multi-function timer 0 input General-purpose port Multi-function timer 1 input General-purpose port Multi-function timer 2 input General-purpose port Multi-function timer 3 input General-purpose port PPG0 trigger input General-purpose port PPG1 trigger input General-purpose port PPG2 trigger input
(Continued)
9
MB91310 Series
Pin no. 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122
Pin name P57 TRG3 P60 ATRG P61 P62 INT0 P63 INT1 P64 INT2 P65 INT3 NMI VDDE VDDI VSS TRST ICLK IBREAK ICS0 ICS1 ICS2 ICD0 ICD1 ICD2 ICD3 P70 P71 P72 P73 P74 X0B VSS
Circuit type C C C O O O O B B C L M M M H H H H I C C C H A General-purpose port PPG3 trigger input General-purpose port
Description
A/D conversion trigger input General-purpose port General-purpose port External interrupt input 0 General-purpose port External interrupt input 1 General-purpose port External interrupt input 2 General-purpose port External interrupt input 3 NMI input 3.3 V power supply 2.5 V power supply Ground DSU tool reset DSU clock DSU break DSU status DSU status DSU status DSU data DSU data DSU data DSU data General-purpose port General-purpose port General-purpose port General-purpose port General-purpose port 48 MHz oscillation pin Ground
(Continued)
10
MB91310 Series
(Continued) Pin no.
123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
Pin name X1B VDDI VDDE UDM UDP UHM UHP B0 B1 B2 G0 G1 G2 R0 R1 R2 VSS VDDI VDDE VOB2 VOB1 DCKO
Circuit type A USB USB D D D D D D D D D D D D 48 MHz oscillation pin 2.5 V power supply 3.3 V power supply USB-Function USB-Function USB-Host USB-Host RGB digital output RGB digital output RGB digital output RGB digital output RGB digital output RGB digital output RGB digital output RGB digital output RGB digital output Ground 2.5 V power supply 3.3 V power supply
Description
Semi Transparent color periodoutput OSD display period output Dot clock output
11
MB91310 Series
s I/O CIRCUIT TYPE
Type
X1
Circuit type Clock input
Remarks * Oscillation circuit
X0
A
STANDBY CONTROL
* CMOS hysteresis input With pull-up resistance
B
Digital input
Digital output Digital output C Digital input
STANDBY CONTROL
* CMOS level output. CMOS level hysteresis input With standby control
2.5 V
Digital output Digital output
* 2.5 V CMOS level output. CMOS level hysteresis input With standby control
D
Digital input
STANDBY CONTROL
(Continued)
12
MB91310 Series
Type
Circuit type
Remarks * Analog input with switch
E Analog input
Input control
* CMOS level input Without standby control
F
Digital input
* CMOS level hysteresis input Without standby control
G
Digital input
Digital output Digital output H Digital input
STANDBY CONTROL
* CMOS level output Hysteresis input Standby control provided Pull-down resistor provided
(Continued)
13
MB91310 Series
Type
Circuit type
Remarks * CMOS level output Hysteresis input Standby control provided Pull-up resistor provided
Digital output Digital output
I
Digital input
STANDBY CONTROL
Open drain control Digital output J Digital input
STANDBY CONTROL
* Open drain output CMOS level hysteresis input With standby control
* Analog pin
K
* CMOS hysteresis input With pull-down resistance
L
Digital input
(Continued)
14
MB91310 Series
(Continued) Type
Circuit type
Remarks * CMOS level output
Open drain control M Digital output
Open drain control Digital output
* Two ports for I2C CMOS hysteresis input CMOS output Stop control provided
Digital input N
Input control
Digital input Open drain control Digital output
* CMOS level output CMOS hysteresis input Digital output O Digital output
Digital input
15
MB91310 Series
s HANDLING DEVICES
* Preventing Latchup Latch-up may occur in a CMOS IC if a voltage greater than VCC or less than VSS is applied to an input or output pin or if an above-rating voltage is applied between VCC and VSS. A latchup,if it occurs, significantly increases the power supply current and may cause thermal destruction of an element. When you use a CMOS IC, be very careful not to exceed the maximum rating. * Treatment of Unused Input Pins Do not leave an unused input pin open, since it may cause a malfunction. Handle by, for example, using a pullup or pull-down resistor. * About Power Supply Pins If there are multiple VCC and VSS pins, from the point of view of device design, pins to be of the same potential are connected the inside of the device to prevent such malfunctioning as latch up. To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply and ground externally. The power pins should be connected to VCC and VSS of this device at the lowest possible impedance from the current supply source. It is also advisable to connect a ceramic bypass capacitor of approximately 0.1F between VCC and VSS near this device. * About Crystal Oscillator Circuit Noise near the X0 and X1 pin may cause the device to malfunction. When designing a PC board using the device, place the X0 and X1 pins, the crystal (or ceramic) oscillator, and the bypass capacitor leading to the ground as close to one another as possible. It is strongly recommended to design PC board so that X0 and X1 pins are surrounded by grounding area for stable operation. * About Mode Pins (MD0 to MD3) These pins should be connected directly to VCC or VSS. To prevent the device erroneously switching to test mode due to noise, design the printed circuit board such that the distance between the mode pins and VCC or V.0 is as short as possible and the connection impedance is low. * About Tool Reset Pin (TRST) This pin must input the same signal as that to INIT when the tool is not used. Apply the same treatment to massproduced products as well. * Operation at Start-up A setting initialization reset (INIT) must always be performed via the INIT pin immediately after the power supply is turned on or recycled. Immediately after the power supply is turned on, hold the Low level input to the INIT pin for the settling time required for the oscillator circuit to take the oscillation stabilization wait time for the oscillator circuit. (For INIT via the INIT pin, the oscillation stabilization wait time setting is initialized to the minimum value.)
16
MB91310 Series
* Oscillation Input at Power-ON When turning the power on, maintain clock input until the device is released from the oscillation stabilization wait state. * Notes on Power-ON/shut-down Cautions to take when turning on/off VDDI (2.5-V internal power supply) and VDDE (3.3-V external-pin power supply) Do not apply VDDE (external) alone continuously (for over an indication of one minute) with VDDI (internal) disconnected not to cause a reliability problem with the LSI. When VDDE (external) returns from the OFF state to the ON state, the circuit may fail to hold its internal state, for example, due to power supply noise. When the power is turned on When the power is turned off VDDI (internal)AnalogVDDE (external)Signal SignalVDDE (external)AnalogVDDI (internal)
* Undefined Output on Power-ON When the power supply is turned on, the output pin may remain indeterminate until the internal power supply becomes stable. * About the attention when the external clock is used When the external clock is used, in principle, supply a clock signal to the X0 (X0A, X0B) pin and an oppositephase clock signal to the X1 (X1A, X1B) pin at the same time. However, In this case. the stop mode must not be used.(This is because, in STOP mode, the X1 (X1A, X1B) pin stops at "H" output.) At 12.5 MHz or less, the device can be used with the clock signal supplied only to the X0 (X0A, X0B) pin. An example of using the external clock is illustrated below.
X0, X0A, X0B X1, X1A, X1B MB91F312A/FV310A
[STOP mode (oscillation stop mode) cannot be used.] External clock usage (normal)
X0, X1A, X1B
X1, X1A, X1B OPEN MB91F312A/FV310A
External clock usage (enabled at 12.5 MHz Max.) Note : The X1 (X1A, X1B) pin must be designed to have a delay within 15 ns, at 10 MHz, from the signal to the X0 (X0A, X0B) pin. 17
MB91310 Series
* Restrictions Common in the MB91310 series (1) Clock Control Block Take the oscillation stabilization wait time during Low level input to the INIT pin. (2) Bit Search Module The 0-detection data register (BSD0), 1-detection data register (BSD1), and transition-detection data register (BSDC) are only word-accessible. (3) I/O Port Ports are accessed only in bytes. (4) Low Power Consumption Mode To enter the standby mode, use the synchronous standby mode (set with the SYNCS bit as bit 8 in the TBCR, or time-base counter control register) and be sure to use the following sequence: (LDI #value_of_standby, R0) (LDI #_STCR, R12) STB R0, @R12 LDUB LDUB NOP NOP NOP NOP NOP In addition, set the I-flag and the ILM and ICR registers to branch to an interrupt handler when the interrupt handler triggers the microcontroller to return from the standby mode. Please do not do the following when the monitor debugger is used. * Set a break point within the above array of instructions. * Single-step the above instructions. (5) Pre-fetch When accessing a prefetch-enabled little endian area, be sure to use word access (in 32-bit, word length) only. Byte or half-word access results in wrong data read. (6) Notes on the PS register As the PS register is processed by some instructions in advance, exception handling below may cause the interrupt handling routine to break when the debugger is used or the display contents of flags in the PS register to be updated. As the microcontroller is designed to carry out reprocessing correctly upon returning from such an EIT event, it performs operations before and after the EIT as specified in either case. 1. The following operations are performed when (c) the instruction followed by a data event or a DIVOU/DIVOS emulator menu instruction (a) receives a user interrupt or NMI or (b) breaks when single-stepped. 18 @R12, R0 @R12, R0 : Write to standby control register (STCR) : STCR lead for synchronous standby : Dummy re-lead of STCR : NOP x 5 for timing adjustment
MB91310 Series
* The D0 and D1 flags are updated in advance. * An EIT handling routine (user interrupt, NMI, or emulator) is executed. * Upon returning from the EIT, the DIVOU/DIVOS instruction is executed and the D0 and D1 flags are updated to the same values as in (1). 2. The following operations are performed when the ORCCR/STILM/MOV Ri and PS instructions are executed. * The PS register is updated in advance. * An EIT handling routine (user interrupt or NMI) is executed. * Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same value as in (1). (7) Watchdog Timer The watchdog timer built in this model monitors a program to check that it defers a reset within a certain period of time. The watchdog timer resets the CPU if the program runs out of controls, preventing the reset defer function from being executed. Once the function of the watchdog timer is enabled, therefore, the watchdog timer keeps on watching programs until it resets the CPU. As an exception, the watchdog timer defers a reset automatically under the condition in which the CPU stops program execution.Refer to the watchdog timer function description for the exceptional condition. If the system runs out of control and develops the above condition, a watchdog reset may not be generated. In that case, please reset (INIT) by external INIT terminal. (8) Notes on using the A/D converter The MB91310 series contains an A/D converter. Supply power to the AVCC at 3.3 V. Unique to the evaluation chip MB91FV310A (1) Simultaneous occurrences of a software break and a user interrupt/NMI If a software break and a user interrupt/NMI occurs simultaneously, the emulator debugger may react as follows. * The debugger stops pointing to a location other than the programmed break points. * The halted program is not re - executed correctly. If this symptom occurs, use a hardware break in place of a hardware break. If you use the monitor debugger, do not set a break point within the relevant array of instructions. (2) Single-stepping of the RETI instruction If an interrupt occurs frequently during single stepping, execute only the relevant processing routine repeatedly after single-stepping RETI. This will prevent the main routine and low-interrupt-level programs from being executed. Do not single-step the RETI instruction for avoidance purposes. When the debugging of the relevant interrupt routine becomes unnecessary, perform debugging with that interrupt disabled. (3) About an Operand Break Do not apply a data event break to access to the area containing the address of a stack pointer. (4) Sample Batch File for Configuration To debug a program downloaded to internal RAM, be sure to execute the following batch file after executing RESET. # Set MODR (0x7fd) = Enable In memory + 16-bit External Bus set mem/byte 0x7fd = 0x5 19
MB91310 Series
s BLOCK DIAGRAM
FR CPU Core
32 32 Flash 512 KB
Bit search
RAM 16 KB
Bus Converter
DMAC 5 ch
32 16 Adapter
External 48 MHz I/F
USB function
USB host
Clock control Interrupt controller
UART 5 ch
Font Flash
OSDC
External interrupt
U-TIMER 5 ch
I 2C 4 ch
A/D 10 ch
Ports
PWC 1 ch
PPG 4 ch
Reload timer 3 ch
Timer 4 ch
20
MB91310 Series
s MEMORY SPACE
1. Memory space
The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access. Direct Addressing Areas The following address space areas are used as I/O areas. These areas are called direct addressing areas, in which the address of an operand can be specified directly during an instruction. The size of directly addressable areas depends on the length of the data being accessed as shown below. byte data access half word data access word data access : 0-0FFH : 0-1FFH : 0-3FFH
2. Memory Map
The figure below shows the memory space of the this item kind. Single chip mode internal ROM external bus mode
0000 0000H I/O 0000 0400H I/O 0001 0000H
Direct Addressing area Refer to I/O Map
0003 C000H 0004 0000H 0005 0000H
Access disallowed Built-in RAM
USB-HOST (REG)
0005 8000H USB-HOST (RAM) 0006 0000H USB-FUNC 0007 0000H MS 0007 8000H OSDC 0008 0000H Flash ROM1 512 KB 0010 0000H 0018 0000H Flash ROM2 512 KB 0020 0000H
Program
Font
External area
FFFF FFFFH
21
MB91310 Series
s I/O MAP
This shows the location of the various peripheral resource registers in the memory space. [How to read the table] Address Register +0 PDR0 [R/W] XXXXXXXX +1 PDR1 [R/W] XXXXXXXX +2 PDR2 [R/W] XXXXXXXX +3 PDR3 [R/W] XXXXXXXX Block T-unit Port Data Register
000000H
Read/Write attribute Initial value after a reset Register name (First-column register at address 4n; second-column register at address 4n + 2) Location of left - most register (When using word access, the register in column 1 is in the MSB side of the data.)
Note:Initial values of register bits are represented as follows: "1" "0" "X" "-" : Initial Value: "1" : Initial Value: "0" : Initial Value: "X" : No physical register at this location
22
MB91310 Series
Address 000000H to 00000FH 000010H 000014H 000018H 00001CH 000020H 000024H 000028H 00002CH 000030H 000034H 000038H 00003CH 000040H 000044H 000048H 00004CH 000050H 000054H 000058H 00005CH
Register +0 PDR0 [R/W] XXXXXXXX PDR4 [R/W] XXXXXXXX ADCTH [R/W] XXXXXX00 +1 PDR1 [R/W] XXXXXXXX PDR5 [R/W] XXXXXXXX ADCTL [R/W] 00000X00 +2 PDR2 [R/W] --XXXXXX PDR6 [R/W] --XXXXXX +3 PDR3 [R/W] -XXXXXXX PDR7 [R/W] ---XXXXX
Block
Reserved
R-bus Port Data Register
ADCH [R/W] 00000000_00000000 ADAT1 [R] XXXXXX00_00000000 ADAT3 [R] XXXXXX00_00000000 ADAT5 [R] XXXXXX00_00000000 ADAT7 [R] XXXXXX00_00000000 ADAT9 [R] XXXXXX00_00000000 ELVR [R/W] 00000000 TMR0 [R] XXXXXXXX XXXXXXXX TMCSR0 [R/W] ----0000 00000000 TMR1 [R] XXXXXXXX XXXXXXXX TMCSR1 [R/W] ----0000 00000000 TMR2 [R] XXXXXXXX XXXXXXXX TMCSR2 [R/W] ----0000 00000000 Reserved Ext int DLYI/I-unit
ADAT0 [R] XXXXXX00_00000000 ADAT2 [R] XXXXXX00_00000000 ADAT4 [R] XXXXXX00_00000000 ADAT6 [R] XXXXXX00_00000000 ADAT8 [R] XXXXXX00_00000000 EIRR [R/W] 00000000 DICR [R/W] -------0 ENIR [R/W] 00000000 HRCL [R/W] 0--11111
10 bit A/D converter
TMRLR0 [W] XXXXXXXX XXXXXXXX TMRLR1 [W] XXXXXXXX XXXXXXXX TMRLR2 [W] XXXXXXXX XXXXXXXX
Reload Timer 0
Reload Timer 1
Reload Timer 2
(Continued)
23
MB91310 Series
Address 000060H 000064H 000068H 00006CH 000070H 000074H 000078H 00007CH 000080H 000084H 000088H 00008CH 000090H 000094H 000098H 00009CH 0000A0H 0000A4H 0000A8H 0000ACH 0000B0H 0000B4H 0000B8H 0000BCH 0000C0H 24
Register +0 SSR [R/W] 00001-00 +1 SIDR [R/W] XXXXXXXX +2 SCR [R/W] 00000100 DRCL [W] -------SCR [R/W] 00000100 DRCL [W] -------SCR [R/W] 00000100 DRCL [W] -------SCR [R/W] 00000100 DRCL [W] -------SCR [R/W] 00000100 DRCL [W] ------- PWCC [R/W] IBSR [R/W] 00000000 ITBA [R/W] ------00 00000000 ISMK [R/W] 01111111 ICCR [R/W] 0-011111 ISBA [R/W] 00000000 IDBL [R/W] -------0 +3 SMR [R/W] 00--0-0UTIMC [R/W] 0--00001 SMR [R/W] 00--0-0UTIMC [R/W] 0--00001 SMR [R/W] 00--0-0UTIMC [R/W] 0--00001 SMR [R/W] 00--0-0UTIMC [R/W] 0--00001 SMR [R/W] 00--0-0UTIMC [R/W] 0--00001
Block UART0 U-TIMER 0 UART1 U-TIMER 1 UART2 U-TIMER 2 UART3 U-TIMER 3 UART4 U-TIMER 4 Reserved
UTIM [R] (UTIMR [W]) 00000000 00000000 SSR [R/W] 00001-00 SIDR [R/W] XXXXXXXX
UTIM [R] (UTIMR [W]) 00000000 00000000 SSR [R/W] 00001-00 SIDR [R/W] XXXXXXXX
UTIM [R] (UTIMR [W]) 00000000 00000000 SSR [R/W] 00001-00 SIDR [R/W] XXXXXXXX
UTIM [R] (UTIMR [W]) 00000000 00000000 SSR [R/W] 00001-00 SIDR [R/W] XXXXXXXX
UTIM [R] (UTIMR [W]) 00000000 00000000 PWCC [R/W] PWCD [R] XXXXXXXX_XXXXXXXX IBCR [R/W] 00000000
PWC
Reserved
ITMK [R/W] 00----11 11111111 IDAR [R/W] 00000000
I2C interface ch0
Reserved
(Continued)
MB91310 Series
Address 0000C4H 0000C8H 0000CCH 0000D0H 0000D4H 0000D8H 0000DCH 0000E0H 0000E4H 0000E8H 0000ECH 0000F0H 0000F4H 0000F8H 0000FCH 000100H 000104H 000108H 00010CH 000110H 000120H 000124H
Register +0 IBCR [R/W] 00000000 +1 IBSR [R/W] 00000000 +2 +3 ITBA [R/W] ------00 00000000 ISMK [R/W] 01111111 ICCR [R/W] 0-011111 ISBA [R/W] 00000000 IDBL [R/W] -------0
Block
ITMK [R/W] 00----11 11111111 IBCR [R/W] 00000000 IDAR [R/W] 00000000 IBSR [R/W] 00000000
I2C interface ch1
Reserved
ITBA [R/W] ------00 00000000 ISMK [R/W] 01111111 ICCR [R/W] 0-011111 ISBA [R/W] 00000000 IDBL [R/W] -------0 Reserved I2C interface ch2
ITMK [R/W] 00----11 11111111 IBCR [R/W] 00000000 IDAR [R/W] 00000000 IBSR [R/W] 00000000
ITBA [R/W] ------00 00000000 ISMK [R/W] 01111111 ICCR [R/W] 0-011111 T0TCR [R/W] 00000000 ISBA [R/W] 00000000 IDBL [R/W] -------0 T0R [R/W] ---00000 I2C interface ch3
ITMK [R/W] 00----11 11111111 T0LPCR [R/W] -----000 IDAR [R/W] 00000000 T0CCR [R/W] 0-010000
T0DRR [R/W] XXXXXXXX XXXXXXXX T1LPCR [R/W] -----000 T1CCR [R/W] 0-000000
T0CRR [R/W] XXXXXXXX XXXXXXXX T1TCR [R/W] 00000000 T1R [R/W] ---00000 Multi-function timer
T1DRR [R/W] XXXXXXXX XXXXXXXX T2LPCR [R/W] -----000 T2CCR [R/W] 0-000000
T1CRR [R/W] XXXXXXXX XXXXXXXX T2TCR [R/W] 00000000 T2R [R/W] ---00000
T2DRR [R/W] XXXXXXXX XXXXXXXX T3LPCR [R/W] -----000 T3CCR [R/W] 0-000000
T2CRR [R/W] XXXXXXXX XXXXXXXX T3TCR [R/W] 00000000 T3R [R/W] ---00000
T3DRR [R/W] XXXXXXXX XXXXXXXX PTMR0 [R] 11111111_11111111 PDUT0 [W] XXXXXXXX_XXXXXXXX
T3CRR [R/W] XXXXXXXX XXXXXXXX Reserved PCSR0 [W] XXXXXXXX_XXXXXXXX PCNH0 [R/W] 00000000 PCNL0 [R/W] 00000000
PPG0
(Continued)
25
MB91310 Series
Address 000128H 00012CH 000130H 000134H 000138H 00013CH 000140H 000144H 000148H 00014CH 000150H 000154H 000158H 00015CH 000160H to 0001FCH 000200H 000204H 000208H 00020CH 000210H 000214H 000218H 00021CH
Register +0 +1 +2 +3
Block
PTMR1 [R] 11111111_11111111 PDUT1 [W] XXXXXXXX_XXXXXXXX PTMR2 [R] 11111111_11111111 PDUT2 [W] XXXXXXXX_XXXXXXXX PTMR3 [R] 11111111_11111111 PDUT3 [W] XXXXXXXX_XXXXXXXX
PCSR1 [W] XXXXXXXX_XXXXXXXX PCNH1 [R/W] 00000000 PCNL1 [R/W] 00000000
PPG1
PCSR2 [W] XXXXXXXX_XXXXXXXX PCNH2 [R/W] 00000000 PCNL2 [R/W] 00000000
PPG2
PCSR3 [W] XXXXXXXX_XXXXXXXX PCNH3 [R/W] 00000000 PCNL3 [R/W] 00000000
PPG3
Reserved
DMACA0 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4 [R/W] 00000000 00000000 00000000 00000000 DMACA1 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4 [R/W] 00000000 00000000 00000000 00000000 DMACA2 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4 [R/W] 00000000 00000000 00000000 00000000 DMACA3 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4 [R/W] 00000000 00000000 00000000 00000000
DMAC
(Continued)
26
MB91310 Series
Address 000220H 000224H 000228H 00022CH to 00023CH 000240H 000244H to 0002FCH 000300H to 0003ECH 0003F0H 0003F4H 0003F8H 0003FCH 000400H 000404H 000408H 00040CH 000410H 000414H 000418H 00041CH 000420H to 00043CH
Register +0 +1 +2 +3
Block
DMACA4 [R/W] 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB4 [R/W] 00000000 00000000 00000000 00000000 DMACR [R/W] 0XX00000 XXXXXXXX XXXXXXXX XXXXXXXX BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR [R] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DDR0 [R/W] 00000000 DDR4 [R/W] 00000000 PFR0 [R/W] 0--00000 PFR4 [R/W] 0------ DDR1 [R/W] 00000000 DDR5 [R/W] 00000000 PFR1 [R/W] 00000000 DDR2 [R/W] --000000 DDR6 [R/W] --000000 PFR2 [R/W] 000---00 DDR3 [R/W] -0000000 DDR7 [R/W] ---00000 PFR3 [R/W] 00000000 Reserved R-bus Port Function Register R-bus Port Direction Register Reserved DMAC
DMAC
Bit Search Module
(Continued)
27
MB91310 Series
Address 000440H 000444H 000448H 00044CH 000450H 000454H 000458H 00045CH 000460H 000464H 000468H 00046CH 000470H to 00047CH 000480H 000484H 000488H 00048CH 000490H
Register +0 ICR00 [R/W] ---11111 ICR04 [R/W] ---11111 ICR08 [R/W] ---11111 ICR12 [R/W] ---11111 ICR16 [R/W] ---11111 ICR20 [R/W] ---11111 ICR24 [R/W] ---11111 ICR28 [R/W] ---11111 ICR32 [R/W] ---11111 ICR36 [R/W] ---11111 ICR40 [R/W] ---11111 ICR44 [R/W] ---11111 +1 ICR01 [R/W] ---11111 ICR05 [R/W] ---11111 ICR09 [R/W] ---11111 ICR13 [R/W] ---11111 ICR17 [R/W] ---11111 ICR21 [R/W] ---11111 ICR25 [R/W] ---11111 ICR29 [R/W] ---11111 ICR33 [R/W] ---11111 ICR37 [R/W] ---11111 ICR41 [R/W] ---11111 ICR45 [R/W] ---11111 RSRR [R/W] 10000000*2 CLKR [R/W] 00000000*1 WPCR [R/W] B 00---000 OSCR [R/W] B 00---000 STCR [R/W] 00110011*2 WPR [W] XXXXXXXX TBCR [R/W] 00XXXX00*1 DIVR0 [R/W] 00000011*1 OSCCR [R/W] XXXXXXX0 CTBR [W] XXXXXXXX DIVR1 [R/W] 00000000*1 +2 ICR02 [R/W] ---11111 ICR06 [R/W] ---11111 ICR10 [R/W] ---11111 ICR14 [R/W] ---11111 ICR18 [R/W] ---11111 ICR22 [R/W] ---11111 ICR26 [R/W] ---11111 ICR30 [R/W] ---11111 ICR34 [R/W] ---11111 ICR38 [R/W] ---11111 ICR42 [R/W] ---11111 ICR46 [R/W] ---11111 +3 ICR03 [R/W] ---11111 ICR07 [R/W] ---11111 ICR11 [R/W] ---11111 ICR15 [R/W] ---11111 ICR19 [R/W] ---11111 ICR23 [R/W] ---11111 ICR27 [R/W] ---11111 ICR31 [R/W] ---11111 ICR35 [R/W] ---11111 ICR39 [R/W] ---11111 ICR43 [R/W] ---11111 ICR47 [R/W] ---11111
Block
Interrupt Control unit
Interrupt Control unit
Clock Control unit
Clock timer Oscillation Stabilization Waiting
(Continued)
28
MB91310 Series
Address 000494H to 0005FCH 000600H 000604H 000608H 00060CH 000610H 000614H 000618H 00061CH 000620H 000624H 000628H to 00063FH 000640H 000644H 000648H 00064CH 000650H 000654H 000658H 00065CH 000660H 000664H 000668H
Register +0 +1 ASR0 [R/W] 00000000 00000000*1 ASR1 [R/W] XXXXXXXX XXXXXXXX*1 ASR2 [R/W] XXXXXXXX XXXXXXXX*1 ASR3 [R/W] XXXXXXXX XXXXXXXX*1 ASR4 [R/W] XXXXXXXX XXXXXXXX*1 ASR5 [R/W] XXXXXXXX XXXXXXXX*1 ASR6 [R/W] XXXXXXXX XXXXXXXX*1 ASR7 [R/W] XXXXXXXX XXXXXXXX*1 AWR0 [R/W] 011111111 11111111*1 AWR2 [R/W] XXXXXXXX XXXXXXXX*1 AWR4 [R/W] XXXXXXXX XXXXXXXX*1 ACR0 [R/W] 1111XX00 00000000*1 ACR1 [R/W] XXXXXXXX XXXXXXXX*1 ACR2 [R/W] XXXXXXXX XXXXXXXX*1 ACR3 [R/W] XXXXXXXX XXXXXXXX*1 ACR4 [R/W] XXXXXXXX XXXXXXXX*1 ACR5 [R/W] XXXXXXXX XXXXXXXX*1 ACR6 [R/W] XXXXXXXX XXXXXXXX*1 ACR7 [R/W] XXXXXXXX XXXXXXXX*1 AWR1 [R/W] XXXXXXXX XXXXXXXX*1 AWR3 [R/W] XXXXXXXX XXXXXXXX*1 AWR5 [R/W] XXXXXXXX XXXXXXXX*1 +2 +3
Block
Reserved
T-unit Port Direction Register
T-unit Port Function Register
Reserved
T-unit
(Continued)
29
MB91310 Series
Address 00066CH 000670H 000674H 000678H 00067CH 000680H 000684H 000684H to 0007F8 H 0007FCH 000800H to 000AFCH 000B00H 000B04H 000B08H 000B0CH 000B10H 000B14H to 000B1CH 000B20H 000B24H 000B28H 000B2CH 000B30H
Register +0 +1 +2 +3 AWR6 [R/W] XXXXXXXX XXXXXXXX*1 IOWR0 [R/W] XXXXXXXX CSER [R/W] 000000001 IOWR1 [R/W] XXXXXXXX CHER [R/W] 11111111 MODR [W] XXXXXXXX ESTS0 [R/W] X0000000 ECTL0 [R/W] 0X000000 ECNT0 [W] XXXXXXXX ESTS1 [R/W] XXXXXXXX ECTL1 [R/W] 00000000 ECNT1 [W] XXXXXXXX ESTS2 [R] 1XXXXXXX ECTL2 [W] 000X0000 EUSA [W] XXX00000 EDTR1 [W] XXXXXXXX XXXXXXXX EIA0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA2 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA3 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA4 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ECTL3 [R/W] 00X00X11 EDTC [W] 0000XXXX TCR [R/W] 00000000 IOWR2 [R/W] XXXXXXXX AWR7 [R/W] XXXXXXXX XXXXXXXX*1
Block
T-unit
Reserved Reserved
EWPT [R] 00000000 00000000 EDTR0 [W] XXXXXXXX XXXXXXXX
DSU
(Continued)
30
MB91310 Series
Address 000B34H 000B38H 000B3CH 000B40H 000B44H 000B48H 000B4CH 000B50H 000B54H 000B58H 000B5CH 000B60H 000B64H 000B68H 000B6CH 000B70H to 000FFCH 001000H 001004H 001008H 00100CH
Register +0 +1 +2 +3
Block
EIA5 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA6 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA7 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EDTA [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EDTM [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOA0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOA1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EPCR [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EPSR [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIAM0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIAM1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOAM0/EODM0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOAM1/EODM1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EOD1 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA0 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMADA0 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMASA1 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMADA1 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX Reserved DSU
DMAC
(Continued)
31
MB91310 Series
Address 001010H 001014H 001018H 00101CH 001020H 001024H 001028H to 006FFCH 007000H 007004H 007008H to 00707CH 007080H to 0070FCH 007100H 007104H 00050000H 00050004H 00050008H 0005000CH 00050010H 00050014H
Register +0 +1 +2 +3
Block
DMASA2 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMADA2 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMASA3 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMADA3 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMASA4 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX DMADA4 [R/W] XXXXXXXX_XXXXXXXX_XXXXXXXX_XXXXXXXX FLCR [R/W] 0110_X000 FLWC [R/W] 0001_0011 Program FLASH I/F Reserved Reserved
DMAC
FNCR [R/W] 0110_X000 FNWC [R/W] 0001_0011
Reserved
FONT FLASH I/F
HR (Hc Revision) [R] 00000000_00000000_00000001_00010000 HC (Hc Control) [R/W] 00000000_00000000_00000000_00000000 HCS (Hc Command Status) [R/W] 00000000_00000000_00000000_00000000 HIS (Hc Interrupt Status) [R/W] 00000000_00000000_00000000_00000000 HIE (Hc Interrupt Enable) [R/W] 00000000_00000000_00000000_00000000 HID (Hc Interrupt Disable) [R/W] 00000000_00000000_00000000_00000000 USB Host
(Continued)
32
MB91310 Series
Address 00050018H 0005000CH 00050020H 00050024H 00050028H 0005002CH 00050030H 00050034H 00050038H 0005003CH 00050040H 00050044H 00050048H 0005004CH 00050050H 00050054H 00050058H 0005005CH to 00057FFFH 00058000H to 00059FFFH 0005A000H to 0005FFFFH
Register +0 +1 +2 +3 HHCCA (Hc HCCA) [R/W] 00000000_00000000_00000000_00000000 HPCED (Hc Period Current ED) [R/W] 00000000_00000000_00000000_00000000 HCHED (Hc Control Head ED) [R/W] 00000000_00000000_00000000_00000000 HCCED (Hc Control Current ED) [R/W] 00000000_00000000_00000000_00000000 HBHED (Hc Bulk Head ED) [R/W] 00000000_00000000_00000000_00000000 HBCED (Hc Bulk Current ED) [R/W] 00000000_00000000_00000000_00000000 HDH (Hc Done Head) [R/W] 00000000_00000000_00000000_00000000 HFI (Hc Fm Interval) [R/W] 00000000_00000000_00101110_11011111 HFR (Hc Fm Remaining) [R] 00000000_00000000_00000000_00000000 HFN (Hc Fm Number) [R] 00000000_00000000_00000000_00000000 HPS (Hc Periodic Start) [R/W] 00000000_00000000_00000000_00000000 HLST (Hc LS Threshold) [R/W] 00000000_00000000_00000110_00101000 HRDA (Hc Rh Descriptor A) [R/W] 00000001_00000000_00000000_00000010 HRDB (Hc Rh Descriptor B) [R/W] 00000000_00000000_00000000_00000000 HRS (Hc Rh Status) [R/W] 00000000_00000000_00000000_000000X0 HRPS1 (Hc Rh Port Status[1]) [R/W] 00000000_00000000_00000000_00000X00 HRPS2 (Hc Rh Port Status[2]) [R/W] 00000000_00000000_00000000_00000X00
Block
USB Host
SRAM 8 KB
(Continued)
33
MB91310 Series
Address 00060000H 00060004H 00060008H 0006000CH to 0006001FH 00060020H 00060024H 00060028H 0006002CH 00060030H 00060034H 00060038H 0006003CH 00060040H 00060044H 00060048H to 0006005FH 00060060H 00060064H 00060068H 0006006CH
Register +0 +1 +2 +3 FIFO0o [R] XXXXXXXX_XXXXXXXX FIFO1 [R] XXXXXXXX_XXXXXXXX FIFO3 [R] XXXXXXXX_XXXXXXXX CONT2 [R/W] XXXXXXXX_XXX00000 CONT4 [R/W] XXXXXXXX_XXX00000 CONT6 [R/W] XXXXXXXX_XXXX00XX CONT8 [R/W] XXXXXXXX_XXX00000 CONT10 [R/W] XXXXXXXX_0XXX0000 TRSIZE [R/W] 00010001_00010001 RSIZE0 [R] XXXXXXXX_XXXX0000 RSIZE1 [R] XXXXXXXX_X0000000 ST2 [R] XXXXXXXX_XXX00000 ST4 [R/W] XXXXX000_00000000 ST3 [R/W] XXXXXXXX_XXX00000 ST5 [R/W] XXXX0XXX_XX00000000 ST1 [R/W] XXXXXX00_00000000 CONT1 [R/W] XXXXX0XX_XXX00000 CONT3 [R/W] XXXXXXXX_XXX00000 CONT5 [R/W] XXXXXXXX_XXXX00XX CONT7 [R/W] XXXXXXXX_XXX00000 CONT9 [R/W] XXXX0000_X000000X TTSIZE [R/W] 00010001_00010001 FIFO0i [W] XXXXXXXX_XXXXXXXX FIFO2 [W] XXXXXXXX_XXXXXXXX
Block
USB Function
(Continued)
34
MB91310 Series
Address 00060070H to 0006007DH 0006007EH 00060080H to 00077FFFH 00078000H 00078004H 00078008H 0007800CH 00078010H 00078014H 00078018H 0007801CH 00078020H 00078024H 00078028H 0007802CH 00078030H 00078034H 00078038H
Register +0 +1 RESET [R/W] 00000---_------- OSD_VADR [R/W] XXXXXXXX_XXXXXXXX OSD_CD2 [R/W] XXXXXXXX_XXXXXXXX OSD_RCD2 [R/W] XXXXXXXX_XXXXXXXX OSD_SOC2 [R/W] XXXXXXXX_XXXXXXXX OSD_HDPC [R/W] XXXXXXXX_XXXXXXXX OSD_SBFCC [R/W] XXXXXXXX_XXXXXXXX OSD_GFCC [R/W] XXXXXXXX_XXXXXXXX OSD_SBCC2 [R/W] XXXXXXXX_XXXXXXXX OSD_SPCC2 [R/W] XXXXXXXX_XXXXXXXX OSD_SPCC4 [R/W] XXXXXXXX_XXXXXXXX OSD_DCLKC1 [R/W] XXXXXXXX_XXXXXXXX OSD_DCLKC3 [R/W] XXXXXXXX_XXXXXXXX OSD_IOC2 [R/W] XXXXXXXX_XXXXXXXX OSD_DPC2 [R/W] XXXXXXXX_XXXXXXXX OSD_DPC4 [R/W] XXXXXXXX_XXXXXXXX OSD_CD1 [R/W] XXXXXXXX_XXXXXXXX OSD_RCD1 [R/W] XXXXXXXX_XXXXXXXX OSD_SOC1 [R/W] XXXXXXXX_0000XXXX OSD_VDPC [R/W] XXXXXXXX_XXXXXXXX OSD_CVSC [R/W] XXXXXXXX_XXXXXXXX OSD_THCC [R/W] XXXXXXXX_XXXXXXXX OSD_SBCC1 [R/W] XXXXXXXX_XXXXXXXX OSD_SPCC1 [R/W] XXXXXXXX_XXXXXXXX OSD_SPCC3 [R/W] XXXXXXXX_XXXXXXXX OSD_SYNCC [R/W] XXXXXXXX_XXXXXXXX OSD_DCLKC2 [R/W] XXXXXXXX_XXXXXXXX OSD_IOC1 [R/W] XXXXXXXX_XXXXXX00 OSD_DPC1 [R/W] XXXXXXXX_XXXXXXXX OSD_DPC3 [R/W] XXXXXXXX_XXXXXXXX OSD_IRC [R/W] XXXXXXXX_XXXXXXXX +2 +3
Block
USB Function
Reserved
OSDC
(Continued)
35
MB91310 Series
(Continued)
Address 0007803CH 00078040H 00078044H 00078048H 0007804CH 00078050H 00078054H 00078058H 0007805CH 00078060H to 0007FFFFH Register +0 +1 +2 +3 Block
OSD_PLT0 [R/W] XXXXXXXX_XXXXXXXX OSD_PLT2 [R/W] XXXXXXXX_XXXXXXXX OSD_PLT4 [R/W] XXXXXXXX_XXXXXXXX OSD_PLT6 [R/W] XXXXXXXX_XXXXXXXX OSD_PLT8 [R/W] XXXXXXXX_XXXXXXXX OSD_PLT10 [R/W] XXXXXXXX_XXXXXXXX OSD_PLT12 [R/W] XXXXXXXX_XXXXXXXX OSD_PLT14 [R/W] XXXXXXXX_XXXXXXXX OSD_ACT1 [R/W] XXXXXXXX_XXXXXXXX
OSD_PLT1 [R/W] XXXXXXXX_XXXXXXXX OSD_PLT3 [R/W] XXXXXXXX_XXXXXXXX OSD_PLT5 [R/W] XXXXXXXX_XXXXXXXX OSD_PLT7 [R/W] XXXXXXXX_XXXXXXXX OSD_PLT9 [R/W] XXXXXXXX_XXXXXXXX OSD_PLT11 [R/W] XXXXXXXX_XXXXXXXX OSD_PLT13 [R/W] XXXXXXXX_XXXXXXXX OSD_PLT15 [R/W] XXXXXXXX_XXXXXXXX OSD_ACT2 [R/W] XXXXXXXX_XXXXXXXX Reserved OSDC
*1 : The initial value of the register varies with the reset level. The initial value shown is the one after an INIT level reset. *2 : The initial value of the register varies with the reset level. The initial value shown is the one after an INIT level reset by the INIT pin.
36
MB91310 Series
s INTERRUPT SOURCE, INTERRUPT VECTOR AND INTERRUPT REGISTER ASSIGNMENT
Interrupt source Reset Mode vector System reserved System reserved System reserved System reserved System reserved Coprocessor absent trap Coprocessor error trap INTE instruction Instruction break exception Operand break trap Step trace trap NMI request (tool) Undefined instruction exception NMI request External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 (USB-function) External interrupt 5 (USB-Host) External interrupt 6 (OSDC) External interrupt 7 Reload timer 0 Reload timer 1 Reload timer 2 UART0(Reception completed) UART1(Reception completed) UART2(Reception completed) UART0 (RX completed) UART1 (RX completed) UART2 (RX completed) Interrupt number 10 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 16 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 Interrupt level 15 (FH) fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 394H 390H 38CH 388H 384H 380H 37CH Address of TBR default 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H 000FFF7CH RN 8 9 10 0 1 2 3 4 5
(Continued)
37
MB91310 Series
Interrupt source DMAC0 (end, error) DMAC1 (end, error) DMAC2 (end, error) DMAC3 (end, error) DMAC4 (end, error) A/D PPG0 PPG1 PPG2 PPG3 PWC System reserved System reserved Main oscillation stabilization Timebase timer overflow System reserved Clock timer I2C ch0 I2C ch1 I C ch2 I C ch3 UART3(Reception completed) UART4(Reception completed) UART3 (RX completed) UART4(Reception completed) timer0 timer1 timer2 timer3 System reserved Delay interrupt source bit System reserved (Used by REALOS) System reserved (Used by REALOS) System reserved
2 2
Interrupt number 10 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 16 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42
Interrupt level ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47
Offset 378H 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H 31CH 318H 314H 310H 30CH 308H 304H 300H 2FCH 2F8H 2F4H
Address of TBR default 000FFF78H 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H 000FFEFCH 000FFEF8H 000FFEF4H
RN
(Continued)
38
MB91310 Series
(Continued)
Interrupt source System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved System reserved Used by INT instruction Interrupt number 10 67 68 69 70 71 72 73 74 75 76 77 78 79 80 to 255 16 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 to FF Interrupt level Offset 2F0H 2ECH 2E8H 2E4H 2E0H 2DCH 2D8H 2D4H 2D0H 2CCH 2C8H 2C4H 2C0H 2BCH to 000H Address of TBR default 000FFEF0H 000FFEECH 000FFEE8H 000FFEE4H 000FFEE0H 000FFEDCH 000FFED8H 000FFED4H 000FFED0H 000FFECCH 000FFEC8H 000FFEC4H 000FFEC0H 000FFEBCH to 000FFC00H RN
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MB91310 Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Parameter Power supply voltage Analog power supply voltage Input voltage Analog pin input voltage Output voltage Storage temperature Symbol VDDE (3.3 V) VDDI (2.5 V) AVCC VI VIA VO Tstg Rating Min Vss - 0.5 Vss - 0.5 Vss - 0.5 Vss - 0.5 Vss - 0.5 Vss - 0.5 - 40 Max Vss + 4.0 Vss + 3.0 Vss + 4.0 Vcc + 0.5 AVcc + 0.5 Vcc + 0.5 + 125 Unit V V V V V V C Remarks
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
2. Recommended Operating Conditions
Parameter Operating temperature Power supply voltage Analog power supply voltage Symbol Ta VDDE (3.3 V) VDDI (2.5 V) AVCC Value Min - 10 3.00 2.30 3.00 Max + 70 3.6 2.70 3.60 Unit C V V Remarks
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
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MB91310 Series
3. DC Characteristics
Parameter Symbol (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 2.5 V 0.2 V, Vss = 0 V) Conditions ROM product during normal operation Ta = + 25 C, fcp = 40 MHz, fcpp = 20 MHz Main sleep mode Ta = + 25 C, fcp = 40 MHz, fcpp = 20 MHz Value Min Typ 200 220 150 170 800 1300 70 570 500 1000 600 1100 VCC x 0.8 VSS VCC - 0.5 VCC - 0.5 VSS -5 1500 VCC VCC x 0.2 VCC x 0.15 VCC VCC 0.4 +5 130 V V V V V V A Between SCL3 and SCL4 Between SDA3 and SDA4 2000 150 650 2000 2500 1000 A A A 200 1500 A 270 180 mA Max 250 mA Unit Remarks MB91F312A Dot clock@90 MHz MB91FV310A Dot clock@90 MHz MB91F312A Dot clock PLL STOP MB91FV310A Dot clock PLL STOP MB91F312A Dot clock PLL stop USB clock stop MB91FV310A Dot clock PLL stop USB clock stop MB91F312A MB91FV310A MB91F312A MB91FV310A MB91F312A Dot clock PLL stop USB clock stop MB91FV310A Dot clock PLL stop USB clock stop
ICC
ICCS
ICCL Power supply
Sub RUN mode Ta = + 25 C, fclk = 32 kHz
ICCH
Main stop mode Ta = + 25 C, fclk = 0 Ta = + 70 C, fclk = 0
ICCT
Clock mode Ta = + 25 C, fclk = 32 kHz
H level input voltage L level input voltage H level output voltage L level output voltage Input leak current I2C bus switch connection resister
VIH VIL
*1 VCC = 3.3 V, *1 VCC = 2.5 V VDDE = 3.3 V, IOH = - 4 mA, *2 VDDE = 2.5 V, IOH = - 4 mA, *3 VDDE = 3.3 V, IOL = 4 mA, *2, *3 Ta = + 70 C
VOH
VOL IIL RBS
*1 : P0 to P7, DOCKI, HSYNC, YSYNC *2 : P0 to P7 *3 : B0 to B2, G0 to B2, R0 to R2, VOB1, VOB2, DCK0, FH 41
MB91310 Series
4. USB
(1) DC Characteristics Symbol VOH VOL (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 2.5 V 0.2 V, Vss = 0 V) Pin Conditions IOH = - 100 A IOL = 100 A Full Speed VOH = VDDE - 0.4 V Low Speed VOH = VDDE - 0.4 V Full Speed VOL = 0.4 V Low Speed VOL = 0.4 V Value Min VDDE - 0.2 0 - 20 -6 20 6 Typ Max VDDE 0.2 mA mA 300 5 mA *1 A *2 Unit Remarks V V
Parameter H level output voltage Output Level Voltage H level output current
IOH
L level output current output short circuit current Input leak current
IOL
IOS ILZ

*1 : About the output short-circuit current IOS The output short-circuit current IOS is the maximum current that flows when the output pin is connected to VDDE or VSS (within the maximum rating). Monitor the short-circuit current H level H output Short-circuited at GND level
3-State Enable "L"
Short-circuited at VDDE level L level L output Monitor the short-circuit current
3-State Enable "L"
About the output short-circuit current: This is the short-circuit current per differential output pin on one side. As this USB I/O buffer is a differential output, consider both of the two pins.
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MB91310 Series
*2 : About Z leakage current ILZ measurement The input leakage current ILZ indicates the leakage current that flows when the VDDE or VSS voltage is applied to the bidirectional pin with the USB I/O buffer in a high impedance state. Monitor the leakage current Z output 0 V, VDD level applied to output pin
3-State Enable "H"
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MB91310 Series
(2) DC characteristics Conforming to the USB Specification Revision 1.1. (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 2.5 V 0.2 V, Vss = 0 V) Parameter "H" level input voltage (driven) "L" level input voltage Diffential Input Sensitivity Differential Common Mode Range "H" level output voltage (driven) "L" level output voltage External Output Signal Crossover Voltage Bus Pull-Up Resistor on Upstream Port Bus Pull-Down Resistor on Downstream Port Termination voltage for upstream port pull-up Symbol VIH VIL VDI VCM VOH VOL VCRS RPU RPD VTERM Value Min 2.0 0.2 0.8 2.8 0.0 1.3 1.425 1.425 3.0 Max 0.8 2.5 3.6 0.3 2.0 1.575 1.575 3.6 Unit V V V V V V V k k V *1 *1 *2 *2 *3 *3 *4 1.5 k 5% 1.5 k 5% *5 Remarks
*1 : About input voltages VIH and VIL The Single-End-Receiver switching threshold voltage of the USB I/O buffer is set within the range of VIL (Max) = 0.8 V and VIH (Min) = 2.0 V (TTL input standard). Appropriate hysteresis is provided to reduce noise sensitivity. *2 : About input voltages VDI and VCM The Differential-Receiver is used to receive USB differential data signals. The Differential-Receiver has a differential input sensitivity of 200 mV when the differential data input remains in the range of 0.8 to 2.5 V to the local ground reference level. The above voltage range is referred to as the common mode input voltage range.
Minimum differential input sensitivity (V)
1.0 (V)
0.2 (V)
0.8 (V)
2.5 (V)
Common mode input voltage(V)
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MB91310 Series
*3 : About output voltages VOL and VOH The output drive capabilities of the driver are 0.3 V or less in Low-State (VOL) (when 1.5 k is loaded at 3.6 V) and 2.8 V or more in High-State (VOH) (when 15 k is loaded at the ground). *4 : About output voltages VCRS The cross voltage of the external differential output signal (D+/D-) of the USB I/O buffer ranges from 1.3 V to 2.0 V.
D+ Max 2.0 (V)
VCRS standard range
Min 1.3 (V) D-
*5 : About termination VTERM VTERM represents the pull-up voltage at the upstream port.
45
MB91310 Series
5. AC Characteristics
(1) Clock Timing (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 2.5 V 0.2 V, Vss = 0 V) Symbol Pin Conditions Value Min Typ Max Unit Remarks
Parameter
Clock frequency
fc
X0, X1
10.135
PLL system (Operation at a maximum internal speed of MHz 40.54 MHz by quadrupling a self-oscillation frequency of 10.135 MHz via PLL) MHz MHz CPU Peripheral
Internal operating clock frequency
fcp fcpp

2.53 2.53

40.54 20.27
(2) Reset
(Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 2.5 V 0.2 V, Vss = 0 V) Symbol Pin Conditions Value Min * tINTL INIT tCP x 5 * Max Unit ns ns ns Remarks
Parameter INIT input time (at power-on) INIT input time (other than at power - on) INIT input time (stop recovery time)
* : INIT input time (at power-on) FAR, CERALOCK : x 215 or greater recommended Crystal : x 221 or greater recommended : Power on X0/X1 period x 2
tINTL
INIT
0.2 VCC
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MB91310 Series
(3) UART timing
(Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 2.5 V 0.2 V, Vss = 0 V) Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX Pin SCK0 to SCK4 SCK0 to SCK4 SO0 to SO4 Conditions Value Min 8 tCYCP* - 80 100 60 4 tCYCP* 4 tCYCP* 60 60 Max + 80 150 Unit ns ns ns ns ns ns ns ns ns Remarks
Parameter Serial clock cycle time SCK SO delay time Valid SI SCK SCK valid SI hold time Serial clock H pulse width Serial clock L pulse width SCK SO delay time Valid SI SCK SCK valid SI hold time
internal shift SCK0 to SCK4 lock mode SI0 to SI4 SCK0 to SCK4 SI0 to SI4 SCK0 to SCK4 SCK0 to SCK4 SCK0 to SCK4 SO0 to SO4 external shift lock mode SCK0 to SCK4 SI0 to SI4 SCK0 to SCK4 SI0 to SI4
* : tCYCP indicates the peripheral clock cycle time. Note : AC characteristic in CLK synchronized mode.
47
MB91310 Series
* Internal shift clock mode
tSCYC
SCK0 to SCK4
VOH VOL VOL
tSLOV
SO0 SO4
VOH VOL
tIVSH VOH VOL
tSHIX VOH VOL
SI0 to SI4
* External shift clock mode
tSLSH VOH
tSHSL
SCK0 to SCK4
VOL
VOL
VOL
tSLOV
SO0 to SO4
VOH VOL
tIVSH VOH VOL
tSHIX VOH VOL
SI0 to SI4
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MB91310 Series
(4) Reload timer clock, PPG timer input, and multi-function timer input timings (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 2.5 V 0.2 V, Vss = 0 V) Parameter Symbol Pin TIN0 to TIN2 PPG0 to PPG3 TRG0 to TRG3 TI0 to TI3 Conditions Value Min Max Unit Remarks
Input pulse width
tTIWH tTIWL
2 tCYCP*
ns
* : tCYCP indicates the peripheral clock cycle time.
tTIWH
tTIWL
(5) Trigger Input Timing
(Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 2.5 V 0.2 V, Vss = 0 V) Symbol tATRG Pin ATRG Conditions Value Min 5 tCYCP* Max Unit ns Remarks
Parameter A/D activation trigger input time
* : tCYCP indicates the peripheral clock cycle time.
tATRG
ATRG
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MB91310 Series
(6) USB interface
(Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 2.5 V 0.2 V, Vss = 0 V) Symbol Pin Conditions Value Min Typ Max Unit Remarks Self-oscillation at a precision of 500 ppm *1 External input at a precision of 500 ppm *1 *2 *2 *2 *2 *2 *2 *3
Parameter
X0B, X1B Input clock Fucyc X0B UHP/UHM UDP/UDM UHP/UHM Fall Time tf UHP/UHM UDP/UDM UHP/UHM Differential Rise and Fall Timing Matching Driver Output Resistance Tfrfm UHP/UHM UDP/UDM UHP/UHM Rzdrv UDP UDM 48 *1 MHz
Rise Time
tr
Full Speed Low Speed Full Speed Low Speed Full Speed Low Speed
4 75 4 75 90 80 28
20 300 20 300 111.11 125 44
ns ns ns ns % %
Fucyc
X0B
UHP UDP UHM UDM 10% tr
90%
90% 10% tf
*1 : The AC characteristics of the USB interface conform to the USB Specification Revision 1.1. *2 : About driver characteristics tr, tf, and Tfrfm These represent the rise (tr) and fall (tf) time standards of the differential data signal. These are defined as times between 10% and 90% of the output signal voltage. For full-speed buffer, the tr/tf ratio is specified to fall within 10% to minimize RFI radiation. 50
MB91310 Series
*3 : About driver characteristic ZDRV USB full-speed connection is made by the twisted pair cable shielded at a characteristic impedance (Z0) of 90 15%. The USB Specification stipulates that the USB driver output impedance be within the range of 28 to 44 . The USB Specification also stipulates that a discrete serial resistor (Rs) be added for balancing purposes while satisfying the above standards. The output impedance of the USB I/O buffer in this LSI is about 3 to 19 . As the serial resistor Rs, therefore, a 25 to 30 type (27 type recommended) should be added.
Rs TxD+ 28 to 44 Equiv. Imped.
Rs TxD- 28 to 44 Equiv. Imped.
3-State
Driver output impedance 3 to 19 Rs 25 to 30 (recommended value: 27 )
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MB91310 Series
(7) Analog RGB
(Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 2.5 V 0.2 V, Vss = 0 V) Symbol Pin ROUT, GOUT, BOUT ROUT, GOUT, BOUT Conditions VREF = 1.1 V, VDDR = VDDG = VDDB = 2.5 V, VRO = 2.7 k, RCOMP = GCOMP = BCOMP = 0.1 F Value Min Typ 5 Max Unit Remarks
Parameter Analog RGB output delay Analog RGB output settling time
tVAD
ns
tVAS
10
ns
* Display signal output timing
DOCKI
tVAD
1 LSB
1 LSB
ROUT GOUT BOUT
tVAS
52
MB91310 Series
(8) Digital RGB Vertical sync, horizontal sync, and display output control signal input timings (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 2.5 V 0.2 V, Vss = 0 V) Parameter Horizontal sync signal cycle time Horizontal sync signal pulse width Horizontal sync signal setup time Horizontal sync signal hold time Vertical sync signal setup time Vertical sync signal hold time Input sync signal rise/fall time Symbol tHCYC tWH tDHST tDHHD tHVST tHVHD tDR tDF Pin HSYNC HSYNC HSYNC VSYNC HSYNC VSYNC Value Min 100 + tWH 20 4 0 5 3 Max 6 1H*2 - 5 5 Unit Dot clock Dot clock s ns ns Dot clock H*2 ns *1 Remarks
*1 : During the horizontal sync signal pulse period, the device stops its internal OSDC operation, disabling writing to the internal VRAM. Therefore, set the horizontal sync signal pulse width and VRAM write cycle to ensure that: horizontal sync signal pulse width < VRAM write cycle. Precisely, adjust the command issuance interval not to issue command 2 or command 4 (VRAM write command) more than once in the horizontal sync signal pulse with period. If the above condition is not satisfied, the device may fail writing to VRAM. *2 : 1H is assumed to be one horizontal sync signal period. * Horizontal sync, and display output control signal input timings
0.8 VDD
DOCKI
0.2 VDD
tDHST
tDHHD
0.8 VDD
0.8 VDD 0.2 VDD
HSYNC
0.2 VDD
tDR, tDF
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MB91310 Series
* Horizontal sync signal input
tHCYC tDF tWH tDR
0.8 VDD
0.8 VDD 0.2 VDD
0.8 VDD 0.2 VDD
HSYNC
* Vertical sync signal input timing * Leading edge of HSYNC
tDF tWH tDR
0.8 VDD
0.8 VDD 0.2 VDD tHVHD tDR
HSYNC
0.2 VDD tDF tHVST
0.8 VDD
0.8 VDD 0.2 VDD
VSYNC
0.2 VDD
*Trailing edge of HSYNC
tDF tWH tDR
0.8 VDD
0.8 VDD 0.2 VDD 0.2 VDD
HSYNC
tDF
tHVST
tHVHD
tDR
0.8 VDD
0.8 VDD 0.2 VDD 0.2 VDD
VSYNC
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MB91310 Series
Display signal timing (Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 2.5 V 0.2 V, Vss = 0 V) Symbol tDIF tDIWH tDIWL tPDC Pin DOCKI DOCKI DCKO R2 to R0, B2 to B0, G2 to G0, VOB1, VOB2 R2 to R0, B2 to B0, G2 to G0, VOB1, VOB2 Value Min 11 3.5 3.5 3 Max 90 8 Unit MHz ns ns ns Remarks *1 *1 *2
Parameter Dot clock input cycle time Dot clock input pulse width Dot clock output delay time 1
Display signal output delay time I1
tPDI1
2
8
ns
*2
Display signal output delay time O1
tPDO1
-4
5
ns
*2
*1 : Input a continuous dot clock signal without a break. *2 : Output load of 16 pF * Display signal output timing
tDIF tDIWH 0.8 VDD tDIWL 0.8 VDD 0.5 VDD 0.2 VDD tPDC tPDC
DOCKI
0.8 VDD
DCKO
tPDO1
0.2 VDD
tPDI1
R2 to R0 G2 to G0 B2 to B0 VOB1, VOB2
0.8 VDD 0.2 VDD
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MB91310 Series
6. 0.25 m Technology About the Power-on Sequence for Dual-power-supply Models
* The power supplies must be turned on in the VDDIAVCC, AVRHVDDE order and off in the VDDEAVCC, AVRHVDDI order. When VDDI is turned on earlier, the potential difference between VDDI and VDDE must be within 3.6 V. * Turn on VDDE before turning on analog power supply AVCC and applying the analog signal.
7. Electrical Characteristics for the A/D Converter
value Min - 5.5 - 3.5
1
(Ta = - 10 C to + 70 C, VDDE = 3.3 V 0.3 V, VDDI = 2.5 V 0.2 V, Vss = AVSS = 0 V, AVRH = 3.0 V to 3.6 V) Parameter Typ 3.6 470 40 Max 10 + 5.5 + 3.5 + 2.0 + 6.0 AVRH + 3.0 5 10 4 Unit bit LSB LSB LSB LSB LSB s mA A A A pF LSB Stop converting AVRH = 3.0 V, AVRL = 0.0 V Stop converting AVcc = 3.3 V, AVRH = 3.3 V (CPU in sleep mode) Remarks
Resolution Total error*1 Nonlinear error*1 Differential linear error* Full transition voltage*1 Conversion time Power supply current (analog + digital) Reference power supply current (between AVRH and AVRL) Analog input capacitance Interchannel disparity *1 : Measured in the CPU sleep state Zero transition voltage*1
- 2.0 - 4.0 AVRH - 5.5 10 *2
*2 : Depends on the clock cycle of the clock signal supplied to peripheral resources. Comparator AN0 to AN9 Analog input pin
RON1 RON2 C0
C1
RON1 = approx. 300 RON2 = approx. 60 C0 = approx. 40 pF C1 = approx. 4 pF
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MB91310 Series
s ORDERING INFORMATION
Part number MB91F312APFV-1xx-BND-E1 MB91FV310APFV-ES Package 144-pin plastic LQFP (FPT-144P-M08) 144-pin plastic LQFP (FPT-144P-M08) Remarks Lead Free Package For development tools
57
MB91310 Series
s PACKAGE DIMENSION
144-pin plastic LQFP (FPT-144P-M08) Note 1) * : Values do not include resin protrusion. Resin protrusion is +0.25 (.010) Max (each side) . Note 2) Pins width and pins thickness include plating thickness. Note 3) Pins width do not include tie bar cutting remainder.
22.000.20(.866.008)SQ
* 20.000.10(.787.004)SQ
108 73
0.1450.055 (.006.002)
109
72
0.08(.003)
Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
INDEX
0~8
0.100.10 (.004.004) (Stand off)
144
37
"A" LEAD No.
1 36
0.50(.020)
0.500.20 (.020.008) 0.600.15 (.024.006)
0.25(.010)
0.220.05 (.009.002)
0.08(.003)
M
C
2003 FUJITSU LIMITED F144019S-c-4-6
Dimensions in mm (inches) Note : The values in parentheses are reference values.
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MB91310 Series
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0311 (c) FUJITSU LIMITED Printed in Japan

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